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Through Silicon Vias (TSV) for Silicon Wafers

   
   

The customer supplies Microplex with silicon wafers with existing through vias and a silicon oxide layer on the wafer surfaces and inside the vias. Our TSV technology utilizes thermal processing in the 600° to 900°C ranges. After the TSV processing, wafers may require CMP to planarize the via pillar to match the silicon surfaces.

The copper conductor we use is optimized to mitigate thermal expansion stresses in a manner that is superior to “plated” copper via technologies. The Microplex via fill technology supports design with high aspect ratios requirements.

   
         
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